The invention relates to technology for designing and verifying an integrated circuit (“IC”) or electronic circuit design.
A semiconductor integrated circuit (IC) or an electronic circuit has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer.
Many phases of physical design may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an electronic circuit, a designer first creates high level behavior descriptions of the electronic circuit device using a high-level hardware design language. An EDA system typically receives the high level behavior descriptions of the electronic circuit device and translates this high-level design language into netlists of various levels of abstraction using a computer synthesis process. A netlist describes interconnections of nodes and components on the chip and includes information on circuit primitives such as transistors and diodes, their sizes and interconnections, for example.
An electronic circuit designer may use a set of layout EDA application programs to create a physical electronic circuit design layout from a logical circuit design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an electronic circuit and to represent electronic circuit components as geometric objects with varying shapes and sizes. After an electronic circuit designer has created an initial electronic circuit layout, the electronic circuit designer then verifies and optimizes the electronic circuit layout using a set of EDA testing and analysis tools. Verification may include, for example, design rule checking to verify compliance with rules established for various electronic circuit parameters.
Typically, geometric information about the placement of the nodes and components onto the chip is determined by a placement process and a routing process. The placement process is a process for placing electronic components or circuit blocks on the chip and the routing process is the process for creating interconnections between the blocks and components according to the specified netlist.
After an electronic circuit designer has created an initial electronic circuit layout, the electronic circuit designer then tests and optimizes the electronic circuit layout using a set of EDA testing and analysis tools. Common testing and optimization steps include extraction, verification, and compaction. The steps of extraction and verification arc performed to ensure that the electronic circuit layout will perform as desired. The test of extraction is the process of analyzing the geometric layout and material composition of an electronic circuit layout in order to “extract” the electrical characteristics of the designed electronic circuit layout. The step of verification uses the extracted electrical characteristics to analyze the circuit design using circuit analysis tools.
Common electrical characteristics that are extracted from an electronic circuit layout include capacitance and resistance of the various “nets” (electrical interconnects) in the electronic circuit. These electrical characteristics are sometimes referred to as “parasitic” since these electrical characteristics are not desired by the designer but result from the underlying physics of the electronic circuit design. For example, when an electronic circuit designer wishes to connect two different locations of an electronic circuit with an electrical conductor, the electrical circuit designer would ideally like a perfect conductor with zero resistance and zero capacitance. However, the geometry of a real conductor, its material composition, and its interaction with other nearby circuit elements will create some parasitic resistance and parasitic capacitance. The parasitic resistance and parasitic capacitance affect the operation of the designed electronic circuit. Thus, the effect of the parasitic resistance and parasitic capacitance on the electrical interconnect must be considered.
To test an electronic circuit layout, the electronic circuit designer ‘extracts’ parasitic resistance and parasitic capacitance from the electronic circuit layout using an extraction application program. Then, the electronic circuit designer analyzes and possibly simulates the electronic circuit using the extracted parasitic resistance and parasitic capacitance information. If the parasitic resistance or parasitic capacitance causes undesired operation of the electronic circuit, then the layout of the electronic circuit must be changed to correct the undesired operation. Furthermore, minimizing the amount of parasitic resistance and parasitic capacitance can optimize the performance of the electronic circuit by reducing power consumption or increasing the operating speed of the electronic circuit.
Based upon this geometric information, photomasks are created for lithographic manufacturing of the electronic product. A photomask, or more simply a “mask,” provides the master image of one layer of a given integrated chip's physical geometries. A typical photolithography system projects UV light energy onto and through the mask in order to transmit the mask pattern in reduced size to the wafer surface, where it interacts with a photosensitive coating on the wafer.
An electronic circuit has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc. that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer. The design of an electronic circuit transforms a circuit description into a geometric description called a layout. The process of converting specifications of an electronic circuit into a layout is called the physical design. After the layout is complete, it is then checked to ensure that it meets the design requirements. The result is a set of design files, which are then converted into pattern generator files. The pattern generator files arc used to produce patterns, or masks, by an optical or electron beam pattern generator. Subsequently, during fabrication of the electronic circuit, these masks are used to pattern chips on the silicon wafer using a sequence of photolithographic steps. Electronic components of the electronic circuit arc therefore formed on the wafer in accordance with the patterns.
Copper interconnect has become the mainstream at 130 nm or beyond because of its advantages over aluminum, such as its lower resistivity and power consumption, and because it is less prone to electromigration. On the other hand, copper interconnect has also brought challenges to manufacturing of electronic circuits because of the effects resulting from the interaction between copper interconnects and the neighboring dielectric materials, especially in the chemical-mechanical polishing (CMP) process. A typical effect comprises thickness or topographical variation due to copper dishing and/or dielectric erosion.
The topographical variation presents an even more profound problem in multi-layer designs, because a topographical variation on a lower layer may be compounded by additional topographical variation(s) above the lower layer, leading to pooling, cracking, and other manufacturing or reliability issues. In order to compensate for the topographical variations, floating or dummy metal fills are typically added into electronic circuit designs to ensure that the electronic circuit designs meet the metal density requirement usually imposed by foundries. The dummy fill shapes have no impact on the behavior and timing of the circuit except for potentially some parasitic impact. Furthermore, there may exist multiple layers for a typical electronic circuit component. At the lower layers, there may exist small undulation or topographical variation caused by these process hotspots. In addition, the undulation on the lower layers may accumulate and compound on top of each other. Therefore, the electronic circuit component may end up with problems such as copper pooling which may lead to shorts between conductors and thus result in significant yield loss.
With the continual effort to shrink the feature size of electronic circuit designs, various model-based, as opposed to rule-based, approaches have been proposed to minimize or better control the thickness variations. A typical rule-based approach essentially applies dummy fill rules under certain circumstances that trigger the application of the dummy fill rules to an electronic circuit design. Some of these dummy fill rules may comprise one or more dummy fill shapes which may be added to the electronic circuit design upon the application of the corresponding dummy fill rules to the electronic circuit design. For example, a rule-based dummy fill approach may comprise a dummy fill rule which requires “maintaining metal density at X percent of the area of interest”. When this rule-based approach is used on an electronic circuit design, the metal density of a portion or even a layer of the electronic design is examined. Where it is determined that the metal density falls below the threshold requirement, the rule-based approach adds one or more dummy fill shapes or even intelligent dummy fill shapes to the portion to maintain the metal density while hoping to address the thickness or topographical variation issues in the electronic circuit design.
On the other hand, a model-based approach takes into account the topographic profiles of the copper layer including the copper layer by electrochemical plating and copper seed layer by a deposition process, and a barrier layer such as a tantalum or a tantalum-nitride layer. Some model-based approaches may even take one or more of the underlying layers into account to evaluate the cumulative effects of a multi-layer electronic circuit design. These model-based approaches yield a more accurate prediction or estimate of the topography and other attributes of the electronic circuit design, which may then be used to guide more accurate methods to fix any critical thickness variations. Since model-based approaches almost always involve intensive computation in simulation, they are usually used during the later stages of the electronic circuit design such as the sign-off/design closure stage.
At and beyond the 65 nm semiconductor manufacturing process node, accurate modeling of systematic and/or random variations in, for example, design layer thickness, which may be caused by various manufacturing processes, such as dry or wet etching, chemical mechanical polishing (CMP), and lithography, may be crucial for achieving higher chip performance, yield, and/or faster time to volume production. In addition, especially in light of the continual shrinking of geometries in the electronic circuit designs, there may exist certain proprietary manufacturing processes or design recipes which may be individually or jointly developed by foundries and “fab-less” design houses in order to ensure the electronic circuit design meets the performance, manufacturing, and or cost metrics. These proprietary manufacturing processes or design recipes further complicate the accuracy of these models.
Traditional design-process interface based on design rules may not capture new design-dependent manufacturing problems that may be introduced with smaller geometries or more complex process stacks. In some cases, electronic circuit designs which pass design rule checks (DRC) may still pose more problems when it comes to manufacturing the electronic circuits according to these electronic circuit designs due to, for example, subsequent processes, such as the chemical mechanical polishing, etching, or resolution enhancement techniques. Such problems or issues may make an electronic circuit or part thereof impossible or difficult to manufacture, reduce the yield, or fail to meet certain performance or cost requirements.
Recent development has introduced physics based modeling to predict or estimate full chip topographic variations caused by CMP processes. Certain electronic design automation (EDA) tools provide the capability of checking for manufacturing intent by using the more accurate physics based models to identify any DRC-like violations such as copper pooling or large step heights between the copper film and the dielectric film. Such problems as copper pooling or excessive thickness or topographic variation may result in short or open circuits within the electronic circuit or may negatively impact timing closure and thus produce detrimental effects on chip yield. For most, if not all of these EDA tools, the hotspot checking is generally provided by the foundries and is sometimes enhanced with certain company- or design-specific checks. These EDA tools then use either model based or rule based metal fill together with other techniques such as wire spreading or wire splitting to at least attempt to address these problems in post-route optimization.
In some electronic circuit manufacturing processes such as chemical mechanical polishing, rule-based or model-based metal fill has been rendered even more difficult due at least in part to long-range effects—other components of the electronic circuit located a few microns or even farther away may negatively affect the topography of any given region.
Nonetheless, recent approaches in hotspot detection and fixing either perform intensive simulation (such as optical simulation based on the Hopkins' formula) or are based on some heuristics or some design rules provided by other rule-based or model-based design checking EDA tools or some other entities (such as the foundries). These approaches are either computation intensive and are thus inherently slow, or are inaccurate due to the nature of the design rules, guidelines, or heuristics. Moreover, some of these recent approaches distinguish between the pre-optical proximity correction (OPC) and post-OPC in terms of hotspot detection and fixing. Some approaches even require the performance of OPC simulation to the pre-OPC layouts, while some other approaches find the correlation and similarity between the pre-OPC and post-OPC stages in terms of the OPC and apply the same simulation for both the pre-OPC and post-OPC hotspot detection and fixing.
For modern electronic circuit designs, it is well known that it is very difficult, if not entirely impossible, to fix all the printability issues with resolution enhancement techniques (RETs) during OPC. These printability issues which the RETs fail to correct during the OPC stage are referred to as lithography hotspots. Similarly, as a result of a manufacturing process, any regions in the electronic circuit design which may not be reliably corrected with existing methods or subsequent manufacturing processes may be referred to as process hotspots. For example, certain film thickness or topographic variation that exceeds certain threshold numbers may be referred to as a CMP hotspot.
It is not uncommon for an electronic circuit design to have problems such as copper pooling on higher layers causing significant yield loss due to the failure to detect and repair various process hotspots on lower layers. This may be the case even if each layer of the electronic circuit design is DRC clean, and metal fill has already been performed for each layer.
Therefore, there exists a need for a method, system, and computer program product for implementing hotspot detection, repair, and optimization of an electronic circuit design which effectively and efficiently resolve the above concerns for all stages of the electronic circuit designs, including the early stages of the electronic circuit design such as floor planning, place and route, and post route optimization.